Vivado simulation (without testbench)

Nov 30, 2023#FPGA192

AI Translation

This post is translated from Chinese into English through AI.View Original

AI-generated summary

The text provides instructions on how to simulate a Vivado project without a testbench. It suggests creating a new project and adding a Verilog file. It also explains how to create a block design file, add modules, and set various parameters. The text mentions running automatic wiring and selecting a clock source. It also explains how to create ports and convert the block design file to a .v file. The text concludes by mentioning that adding a simulation clock module may cause errors during RTL analysis and synthesis. The author acknowledges being a beginner in using Vivado and welcomes any corrections.

Vivado Simulation (No Testbench)#

Implementation Steps#

Create a new project and add your own Verilog file

After adding, Vivado will automatically recognize the module in the file.

Create a block design file and add modules

There may be the following warnings before adding, wait for a while.

Right-click again and click "Add IP" to add the following modules

Double-clicking on this module allows you to set various parameters

Run auto-connection and select the clock source added above

Right-click on the floating pin and select the following option to create a port

In the left source column, right-click at 1 and select the option at 2 to convert the bd file to a .v file

Right-click on the generated new file and set it as the top file

Run the simulation and you can see the simulation results

Summary#

If the simulation clock module is added, there may be errors when performing RTL analysis and synthesis. It is estimated that this module can only be used for behavioral-level simulation.

Since I have just started using Vivado and I am not familiar with many operations, please feel free to correct any mistakes.